Digital Verification Engineer

Job overview

The Digital Verification Engineer is an onsite role based in San Jose, CA, with an annual salary range of $135,400 to $216,600. This position supports the test and automation solutions at Teradyne, focusing on FPGA verification projects. This role exists to plan and execute functional verification strategies for complex electronic systems. The engineer works under technical supervision to interface with hardware and software teams, ensuring that Teradyne's test technology meets performance standards through rigorous constraint-random testing and UVM-based verification.

What you'll do

• Plan and execute FPGA verification projects
• develop UVM testbench components and sequences
• integrate verification IP
• develop reference models
• interface with hardware/software teams
• bring issues to closure.

What we're looking for

Skills & competencies

full-time

day shift

san jose ca

teradyne

fpga

verification

digital

uvm

systemverilog

automation

engineering

$135k-$216k/yr

Work arrangement

• Weekend coverage required

Benefits & perks

• Discretionary bonus, medical/dental/vision insurance, 401(k), life/disability insurance, PTO, tuition assistance.

About the employer

Teradyne is hiring for this role. Industry: Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals. Sector: 33.