Design For Test Engineer IV (IC)
Compensation
$112k – $171k /yr
Employment type
Full-time
Work setting
On-site
Location
San Jose, CA
Schedule
Day shift
Posted
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Job overview
The Design For Test Engineer IV is an onsite role based in San Jose, CA. The compensation range is $112,200-$170,500 per year, and the role supports the engineering services team at Arrow Electronics, Inc. This role exists to implement DFT strategies for high-end networking chips. The engineer performs scan-insertion, ATPG pattern generation, and silicon debug to ensure high-quality test coverage for complex SoCs.
What we're looking for
- Skills & competencies
- full-timeday shiftdftengineersan jose caarrow electronicseinfochips$112.2k-$170.5k/yrsocatpgmbistjtagnetworking
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, dental, vision, 401(k) with match, tuition reimbursement, PTO
About the employer
Arrow Electronics, Inc. is hiring for this role. Industry: Engineering Services. Sector: 54.
Additional details
- Industry sector
- 54
- Industry
- Engineering Services
- Occupation code
- 17-2061.00
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Listing ID: f0ae7494-49d5-47a0-8701-44a4e689e558