Senior Packaging Engineer (Semiconductor Test)

Job overview

The Senior Packaging Engineer (Semiconductor Test) is an onsite role based in North Reading, MA, with a salary range of $175,300–$280,600 per year. This position supports the Semiconductor Test Division by providing technical direction for package electrical integrity and interconnect strategy. The role exists to ensure the physical realization of complex RF, analog, and mixed-signal ASIC products. It contributes to the team by balancing electrical performance, manufacturability, and cost through advanced simulation and cross-functional collaboration.

What you'll do

• Lead ASIC package signal and power integrity architecture
• develop package and PCB layout constraints
• collaborate with cross-functional teams to identify technical risks
• build time-domain and frequency-domain models
• support power distribution network planning
• mentor engineers in package design methods.

What we're looking for

Skills & competencies

full-time

day shift

north reading ma

semiconductor

packaging engineer

signal integrity

power integrity

asic

engineering

teradyne

$175k-$280k

Work arrangement

• Weekend coverage required

Benefits & perks

• Medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance.

Why this role

Requires extensive experience in semiconductor package design and SI/PI analysis for high-performance mixed-signal applications.

About the employer

Teradyne is hiring for this role. Industry: Engineering Services. Sector: 54.