SOC Top Level Physical Design Engineer, Annapurna Labs

Job overview

The SOC Top Level Physical Design Engineer role is an onsite position based in Cupertino, CA. Compensation is not specified in the posting, and this role supports the Annapurna Labs team in designing custom SoCs for AWS machine learning servers. This role exists to drive full-chip floorplanning, integration, and tapeout. The engineer will define and optimize physical verification methodologies to ensure high design quality.

What you'll do

• Drive full-chip floorplan, placement, integration, PV signoff, and tapeout.
• Collaborate with the front-end team to understand RTL and drive physical aspects.
• Define and execute physical verification methodologies using industry-standard EDA tools.
• Perform DRC, LVS, and PERC verification.
• Debug and resolve physical verification issues.
• Interface with foundries for rule deck updates.

What we're looking for

Skills & competencies

full-time

cupertino ca

physical design

soc

asic

machine learning

hardware engineering

tapeout

onsite

no on-call

no travel

Work arrangement

• Weekend coverage required

Benefits & perks

• Health insurance, 401(k) matching, paid time off, parental leave, sign-on payments, and RSUs.

Why this role

Focus on full-chip physical design and tapeout for advanced nodes.

About the employer

Annapurna Labs (U.S.) Inc. is hiring for this role. Industry: Engineering Services. Sector: 54.