ASIC/FPGA Design Verification Engineer

Job overview

The ASIC/FPGA Design Verification Engineer is an onsite role based in North Reading, MA, with a base salary range of $123,100 - $196,900 per year. This role is part of the Logic Design Engineering (LDE) team. This position exists to verify FPGA designs and ensure high-quality, robust product delivery. The engineer works closely with cross-functional teams to develop testbench architectures, write tests, and close functional coverage.

What you'll do

• Review design requirements
• write verification plans
• develop testbench architecture
• create reference models
• write System Verilog tests
• develop UVM environments
• perform debug
• collect and close functional/code coverage
• collaborate with logic designers.

What we're looking for

Experience

5+ years of professional experience in digital logic verification or related roles

Skills & competencies

full-time

day shift

north reading ma

teradyne

asic

fpga

verification

no weekends

no on-call

$123k-$196k

Work arrangement

• Visa sponsorship: No

About the employer

Teradyne is hiring for this role. Industry: Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals. Sector: 33.