Principal FPGA / RTL Design Engineer
Compensation
$165k – $250k /yr
Employment type
Full-time
Work setting
On-site
Location
Irvine, CA
Schedule
Day shift
Posted
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Job overview
The Principal FPGA / RTL Design Engineer is an onsite role based in Irvine, CA, with a salary range of $165,000-$250,000 per year. Silvus Technologies provides advanced communications systems for mission-critical applications. This role leads the implementation of signal processing algorithms for MIMO wireless networking products. The engineer participates in all aspects of the research and development process, from concept to field deployment.
What you'll do
- Architect digital designs
- perform RTL coding and simulation
- manage FPGA synthesis and timing closure
- conduct hardware verification
- support RF and software teams.
What we're looking for
- Education
- Bachelor of Science degree
- Experience
- Bachelor's degree and 10 years of experience in RTL design and FPGA implementation.
- Skills & competencies
- full-timeirvine casilvus technologiesfpgartlsignal processingverilogonsitedefense$165k-$250k
- Work arrangement
- Visa sponsorship: No
About the employer
Silvus Technologies is hiring for this role. Industry: Radio and Television Broadcasting and Wireless Communications Equipment Manufacturing. Sector: 33.
Additional details
- Industry sector
- 33
- Industry
- Radio and Television Broadcasting and Wireless Communications Equipment Manufacturing
- Occupation code
- 17-2072.00
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Listing ID: dc18873e-a57e-4b0d-bcf3-2b265df00480