Verification Engineer

Job overview

The Verification Engineer role is onsite in Austin, TX. Compensation is not specified. The posting describes a 12-month position. The work focuses on formal verification and design verification methods. The engineer applies formal verification techniques to assess hardware designs and their properties. The listed preferred experience includes formal verification tools and applications, assertion-based specifications, scripting for flow automation, and SystemVerilog and UVM methodologies.

What you'll do

• Use formal verification experience and tools such as VC Formal or Jasper Gold
• apply SystemVerilog Assertions and formal property specification
• work with formal verification applications including FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
• use TCL, Python, or Perl for flow automation
• apply design verification experience focused on formal verification. SystemVerilog and UVM experience is listed as nice to have.

What we're looking for

Skills & competencies

verification engineer

formal verification

austin tx

systemverilog assertions

sva

vc formal

jasper gold

fpv

connectivity checking

register verification

equivalence checking

tcl python perl

Work arrangement

• Weekend coverage required

Why this role

Preferred experience includes Synopsys VC Formal or Cadence Jasper Gold, formal verification applications, and scripting languages for automation.

About the employer

Sunrise Systems Inc is hiring for this role. Industry: Engineering Services. Sector: 54.