Staff Design Verification Engineer – Mixed-Signal Automotive Power

Job overview

The Staff Design Verification Engineer role is onsite in Plano, Texas. Compensation is not specified; the posting references a competitive benefits package. The role supports Renesas’ development of mixed-signal automotive power-management devices, including PMICs, switching regulators, and analog IP. The engineer builds verification environments and plans, runs simulations, and investigates design issues across analog and digital domains. The work helps design, systems, validation, and CAD teams verify complex power chips and achieve development sign-off against functional and automotive requirements.

What you'll do

• Architect mixed-signal verification environments, including RNM and AMS model integration
• develop verification plans for automotive PMICs
• debug analog blocks
• set up and optimize gate-level simulation flows
• run RTL and gate-level simulations across PVT corners
• collaborate with design, application engineering, ATE, and silicon validation teams
• troubleshoot analog/digital interactions
• improve verification tools and methods
• maintain verification documentation, test plans, and coverage metrics.

What we're looking for

Skills & competencies

design verification engineer

mixed-signal verification

automotive pmic

plano tx

renesas

rnm

ams

gate-level simulation

rtl

systemverilog

uvm

power management

Work arrangement

• Weekend coverage required

Benefits & perks

• Competitive benefits package
• details provided during the hiring process.

Why this role

Requires an MS or Ph.D. and 8+ years of mixed-signal or analog verification experience. Relevant methods and tools include RNM, AMS, Spectre, Xcelium, GLS, Verilog, SystemVerilog, SPICE, and UVM.

About the employer

Renesas is hiring for this role. Industry: Engineering Services. Sector: 54.