Principal Digital Design Engineer / Chip Lead
Compensation
$178k – $389k /yr
Employment type
Full-time
Work setting
On-site
Location
San Jose, CA
Schedule
Day shift
Posted
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Job overview
The Principal Digital Design Engineer / Chip Lead is an onsite role based in San Jose, CA. The annual base salary range is $178,000 to $389,000, and this position supports Micron Technology's Interface Pathfinding team. This role serves as the technical anchor for a small, senior team focused on high-speed interface innovations. The engineer owns chip architecture, RTL design, and tape-out processes for novel PHY solutions.
What you'll do
- Define top-level chip architecture
- author and maintain synthesizable RTL
- develop chip-level timing constraints
- drive logic synthesis
- coordinate verification
- manage IP integration
- own tape-out checklist sign-off
- author architecture specifications.
What we're looking for
- Skills & competencies
- full-timeday shiftsan jose camicron technologydigital designchip leadasicphyrtltape-outsemiconductor$178k-$389k/yr
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, dental, vision, paid family leave, paid time-off, 401(k).
Why this role
Requires 10+ years of ASIC/digital design experience and at least one prior tape-out in a lead role.
About the employer
Micron Technology, Inc. is hiring for this role. Industry: Computer Systems Design Services. Sector: 54.
Additional details
- Industry sector
- 54
- Industry
- Computer Systems Design Services
- Occupation code
- 17-2061.00
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Listing ID: a7337b8b-a4a8-4637-928c-72ce4c6bb5ce