Principal Design-for-Test Engineer

Job overview

The Principal Design-for-Test Engineer role is onsite at a customer location in Santa Clara, CA. Compensation is not specified. The role supports system-on-chip design-for-test implementation and validation in a client environment. The engineer applies advanced scan, automatic test pattern generation, and memory built-in self-test expertise to implement and validate test flows. The work contributes to test coverage and reliable verification of system-on-chip designs.

What you'll do

• Perform scan insertion and ATPG validation for system-on-chip designs
• work with Tessent and Modus for stuck-at and transition fault models, coverage analysis, and test point insertion
• support scan and ATPG improvements, MBIST insertion, and scan insertion flows using FC Compiler and Design Compiler
• debug ATPG gate-level simulations
• support SSN pattern retargeting and FC/SOC gate-level validation
• use relevant Tessent, Synopsys, and Cadence tools.

What we're looking for

Skills & competencies

principal design-for-test engineer

dft

scan insertion

atpg

mbist

soc validation

tessent

modus

gate-level simulation

santa clara ca

onsite

yantran

Work arrangement

• Weekend coverage required

Why this role

Day-one onsite at customer location; 8–12 years of experience specified.

About the employer

Yantran LLC is hiring for this role. Industry: Engineering Services. Sector: 54.