Silicon Physical Design Engineer V, ASIC Power

Job overview

The Silicon Physical Design Engineer V role is hybrid in Sunnyvale, CA, with compensation of $125.00–$129.27 per hour. The listing describes the desired location as remote in the Pacific time zone and identifies work on Meta AR/VR products.

What you'll do

• Set up and maintain RTL and gate-level power analysis flows
• generate and manage simulation activity inputs
• correlate power estimates and explain differences
• produce power breakdowns and identify contributors
• evaluate power-reduction opportunities
• automate flows and reporting
• perform PPA optimization and ASIC power analysis
• and document methodology for design teams.

What we're looking for

Skills & competencies

silicon physical design engineer v

asic power

power analysis

power optimization

ar/vr

pprtl

ptpx

fusion compiler

tcl

python

sunnyvale ca

mindlance

$125-$129.27/hr

Work arrangement

• Weekend coverage required

Why this role

The work centers on ASIC power analysis and optimization for AR/VR products, using tools and flows such as PPRTL, PTPX, Fusion Compiler, TCL, and Python.

About the employer

Mindlance is hiring for this role. Industry: Engineering Services. Sector: 54.