FPGA Engineering Manager (San Jose, CA)
Compensation
$171k – $274k /yr
Employment type
Full-time
Work setting
On-site
Location
San Jose, CA
Schedule
Day shift
Posted
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Job overview
The FPGA Engineering Manager is an onsite role based in San Jose, CA, with a salary range of $171,000–$273,600 USD per year. This position oversees the development of memory test solutions. This role exists to provide technical oversight and project management for FPGA development. It contributes to the company's goals by delivering high-quality, reliable products for advanced memory technologies.
What you'll do
- Plan/manage FPGA development projects
- represent the team on project core teams
- provide sustaining support
- work with cross-functional teams
- recruit/onboard talent
- set goals
- provide technical guidance
- contribute to FPGA design.
What we're looking for
- Skills & competencies
- full-timeday shiftsan jose cateradynemanagementfpgamemory testsemiconductoronsiteno on-call$171k-$273k/yr
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, dental, vision, FSA, retirement savings, life/disability insurance, paid vacation/holidays, tuition assistance.
Why this role
Requires 12+ years in digital ASIC or FPGA design and 5+ years of project lead experience.
About the employer
Teradyne is hiring for this role. Industry: Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals. Sector: 33.
Additional details
- Industry sector
- 33
- Industry
- Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals
- Occupation code
- 15-1252.00
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Listing ID: 8de263d2-17a0-4e36-be98-0a8f99db6fd3