Design For Test Engineer IV
Compensation
$112k – $171k /yr
Employment type
Full-time
Work setting
On-site
Location
San Jose, CA
Schedule
Day shift
Posted
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Job overview
The Design For Test Engineer IV role is an onsite position based in San Jose, CA. The salary range is $112,200 – $170,500 per year, and the role supports Arrow Electronics, Inc. in delivering DFT deliverables for complex semiconductor designs. This role exists to lead DFT activities, including scan insertion, JTAG, and ATPG coverage analysis. The engineer solves complex problems, collaborates with cross-site design teams, and implements new methodologies to improve product quality and testing efficiency.
What you'll do
- Responsible for scan insertion, JTAG, and ATPG
- Perform coverage analysis and simulation debug
- Ensure successful delivery of DFT deliverables
- Debug and find root causes for simulation failures
- Collaborate to enhance DFT best practices
- Lead project teams and train junior staff.
What we're looking for
- Skills & competencies
- full-timeday shiftsan jose caarrow electronicsdft engineersemiconductorengineeringdesign for testjtagatpg$112k-$170k
- Work arrangement
- Weekend coverage required
Benefits & perks
- Competitive salary, health benefits, 401k with match, disability insurance, paid time off, tuition reimbursement.
Why this role
Senior-level role with opportunities to lead and mentor.
About the employer
Arrow Electronics, Inc. is hiring for this role. Industry: Engineering Services. Sector: 54.
Additional details
- Industry sector
- 54
- Industry
- Engineering Services
- Occupation code
- 17-2061.00
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Listing ID: 81a1e2c6-32ea-4c28-9b23-ce4dbb6f1df3