Physical Design Engineer - Static Timing Analysis, Annapurna Labs

Job overview

The Physical Design Engineer - Static Timing Analysis role is an onsite position based in Cupertino, CA. The base salary range is $157,300.00 - $212,800.00 USD annually, and this role supports the Annapurna Labs team in developing machine learning acceleration hardware. This role exists to develop and maintain flows for block and full-chip level static timing analysis. The engineer writes, debugs, and validates timing constraints and provides guidance on fixing timing issues.

What you'll do

• Develop & maintain flows for static timing analysis
• Write, debug & validate timing constraints
• Run Static Timing Analysis
• Provide guidance on how to fix timing issues
• Develop scripts to automate running timing analysis.

What we're looking for

Skills & competencies

full-time

day shift

cupertino ca

annapurna labs

physical design

static timing analysis

asic

machine learning

hardware

$157k-$212k/yr

Work arrangement

• Weekend coverage required

Benefits & perks

• Health insurance, 401(k) matching, paid time off, parental leave, sign-on payments, RSUs

Why this role

Requires expertise in timing analysis fundamentals.

About the employer

Annapurna Labs (U.S.) Inc. is hiring for this role. Industry: Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services. Sector: 51.