MTS SoC Design for Test Engineer, High Bandwidth Memory

Job overview

MTS SoC Design for Test Engineer, High Bandwidth Memory is an onsite role in Folsom, CA. The stated annual base pay range is $199,000–$347,000. The role supports Micron’s Heterogeneous Integration Group, which develops High Bandwidth Memory solutions for AI and machine-learning applications. The engineer owns design-for-test architecture and implementation for complex HBM base-die system-on-chip designs. The work enables manufacturability, quality, and silicon bring-up by integrating test structures, completing signoff flows, and coordinating with design, physical-design, verification, product, and manufacturing teams.

What you'll do

• Own SoC-level scan, MBIST, applicable LBIST, boundary-scan/JTAG, and test-access structures
• define DFT architecture early in design
• implement and integrate DFT logic at block, subsystem, and full-chip levels
• complete lint, CDC, DFT-rule, ATPG-readiness, and coverage-closure flows
• collaborate on placement, routing, timing, and DRC/LVS signoff
• support testability, debug, and silicon bring-up
• improve DFT workflows using Gen-AI and Agentic-AI solutions.

What we're looking for

Skills & competencies

mts engineer

soc dft

high bandwidth memory

hbm

scan

mbist

atpg

rtl-to-gds

semiconductor

folsom ca

micron

$199k–$347k/year

Work arrangement

• Weekend coverage required

Benefits & perks

• Medical, dental, and vision plan options
• income-protection programs
• paid family leave
• paid time off and paid holidays.

Why this role

Leads DFT for HBM base-die designs and applies generative and agentic AI to DFT workflows.

About the employer

Micron Technology, Inc. is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.