ASIC Design Engineer, Machine Learning Acceleration

Job overview

The ASIC Design Engineer, Machine Learning Acceleration role is an onsite position based in Cupertino, CA or Austin, TX. Compensation is not specified in the posting, and this role supports the Annapurna Labs team in designing custom SoCs for AWS machine learning servers. This role exists to develop and optimize high-performance hardware for data centers. The engineer will create microarchitectures, implement RTL, and ensure design integrity to meet project specifications for power, performance, and area.

What you'll do

• Develop and implement high-performance, area and power-efficient RTL designs.
• Conduct in-depth analysis of designs and microarchitectures to optimize trade-offs.
• Create microarchitectures and deliver synthesis and timing-clean designs.
• Execute lint and clock domain crossing quality checks.
• Collaborate with cross-functional teams including architects, verification specialists, and back-end experts.

What we're looking for

Skills & competencies

full-time

cupertino ca

austin tx

asic design

systemverilog

machine learning

hardware engineering

rtl

onsite

no on-call

no travel

Work arrangement

• Weekend coverage required

Benefits & perks

• Health insurance, 401(k) matching, paid time off, parental leave, sign-on payments, and RSUs.

Why this role

Focus on cloud-scale machine learning acceleration hardware design.

About the employer

Annapurna Labs (U.S.) Inc. is hiring for this role. Industry: Custom Computer Programming Services. Sector: 54.