Design For Test Engineer III (IC)
Compensation
$96k – $171k /yr
Employment type
Full-time
Work setting
On-site
Location
San Jose, CA
Schedule
Day shift
Posted
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Job overview
The Design For Test Engineer III (IC) is an onsite role based in San Jose, CA, with a salary range of $95,900.00 - $170,500.00 per year. This position supports the eInfochips division of Arrow Electronics, Inc. in the development of advanced semiconductor chips. The role exists to implement Design For Test (DFT) strategies for high-performance networking chips. By ensuring testability at the design stage, the engineer enables efficient manufacturing and silicon bring-up, contributing to the company's mission of accelerating connected product innovation.
What you'll do
- Implement DFT for networking chips
- perform scan-insertion and ATPG
- conduct pattern simulations
- manage MBIST insertion and verification
- perform silicon debug.
What we're looking for
- Skills & competencies
- full-timeday shiftsan jose caarrow electronicseinfochipsdftsemiconductornetworking chipsatpgmbist$95k-$170k/yr
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, Dental, Vision Insurance, 401k with matching, Short-Term/Long-Term Disability, HSA/HRA options, Paid Time Off, Tuition Reimbursement.
Why this role
Specialization in 3nm/5nm chips; partnership with major tech firms like Qualcomm and NVIDIA.
About the employer
Arrow Electronics, Inc. is hiring for this role. Industry: Engineering Services. Sector: 54.
Additional details
- Industry sector
- 54
- Industry
- Engineering Services
- Occupation code
- 17-2072.00
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Listing ID: 5e0f2770-02ef-4838-bd01-813b83e4e197