Layout Engineer
Employment type
Full-time
Work setting
On-site
Location
Boise, ID
Schedule
Day shift
Posted
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Job overview
The Layout Engineer is an onsite role based in Boise, ID. Compensation is not specified for this position, which supports the DRAM Engineering Group (DEG) in building physical design foundations for memory technologies. This role exists to shape block-level layouts and guide physical design strategy. By ensuring DRC, LVS, and reliability compliance, the engineer directly influences the quality and performance of DRAM products.
What you'll do
- Build block-level layouts in Cadence Virtuoso.
- Apply physical constraints such as PDN and pin placement.
- Ensure DRC, LVS, and density compliance.
- Support parasitic extraction and post-layout verification.
What we're looking for
- Skills & competencies
- full-timeday shiftboise idmicronlayoutcadence virtuosodramphysical designsemiconductoronsiteno on-call
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, dental, and vision plans, paid family leave, paid time-off, and paid holidays.
Why this role
Focus on block-level physical design for DRAM.
About the employer
Micron Technology, Inc. is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.
Additional details
- Industry sector
- 33
- Industry
- Semiconductor and Related Device Manufacturing
- Occupation code
- 17-2071.00
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Listing ID: 5ad8335b-775b-4c2a-8c96-3658bcef0526