PD Engineer

Job overview

The PD Engineer is an onsite role based in Santa Clara, CA, with a pay range of $107,400 to $161,200 per year. This position supports the ASICS Engineering group at Qualcomm Atheros by working on the physical design flow for high-speed, low-power designs. The role exists to implement and deliver complex physical design solutions. It contributes to the team by performing floorplanning, timing closure, and power analysis to ensure the successful tapeout of connectivity SoCs.

What you'll do

• Develop tiles level physical design
• Enable low power implementation
• Perform floorplanning and power planning
• Conduct IR drop analysis
• Perform timing optimization and closure
• Debug physical violations.

What we're looking for

Skills & competencies

contract

day shift

santa clara ca

qualcomm

physical design

asic

soc

timing

floorplanning

innovus

$107.4k-$161.2k/yr

Work arrangement

• Weekend coverage required

Benefits & perks

• Competitive annual discretionary bonus program, RSU grants, and comprehensive benefits package.

Why this role

Requires experience with Cadence Innovus or Synopsys Fusion Compiler.

About the employer

Qualcomm is hiring for this role. Industry: Engineering Services. Sector: 54.