Principal Design Verification Engineer

Job overview

The Principal Design Verification Engineer role is onsite in Chandler, AZ. Compensation is not specified. Renesas develops embedded semiconductor solutions for automotive, industrial, infrastructure, and IoT applications. The engineer leads verification strategy and execution for complex semiconductor designs, including next-generation memory interface products. The role works with design teams to verify functionality and performance, close coverage, resolve issues, and prepare products for signoff.

What you'll do

• Lead block- and system-level verification strategy and execution
• define methodologies, test plans, coverage strategies, and environments
• develop and optimize SystemVerilog/UVM testbenches
• drive test development, functional coverage, debugging, and coverage closure
• partner with RTL and design engineers
• develop reusable verification components
• lead process improvements
• participate in technical reviews
• and mentor verification engineers.

What we're looking for

Skills & competencies

principal design verification engineer

chandler az

renesas

semiconductor verification

systemverilog

uvm

ddr6

memory interfaces

functional coverage

testbench development

technical leadership

silicon design

Work arrangement

• Weekend coverage required

Benefits & perks

• Competitive benefits package
• further information is provided during the hiring process.

Why this role

The posting highlights next-generation DDR6 technology and lists DDR or memory-interface experience as an advantage, not a requirement.

About the employer

Renesas is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.