Senior FPGA Design Engineer (MTD, Tualatin, OR)

Job overview

The Senior FPGA Design Engineer is an onsite role based in Tualatin, OR, with a base salary range of $154,900-$247,800 per year. This position supports Teradyne's Memory Test Division by developing cutting-edge memory test solutions for next-generation technologies. This role exists to architect and implement high-performance FPGA solutions for Flash and DRAM test instrumentation. The engineer will provide technical leadership, turn abstract requirements into reliable designs, and collaborate with cross-functional teams to ensure high-quality product delivery.

What you'll do

• Architect and implement FPGA solutions for Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers.
• Turn abstract concepts into reliable, extensible designs.
• Assist in maintenance and extension of existing FPGA designs.
• Maintain schedule commitments and deliver high-quality end products.

What we're looking for

Skills & competencies

full-time

day shift

tualatin or

teradyne

fpga

digital design

rtl

asic

memory test

senior level

$154k-$248k

Work arrangement

• Weekend coverage required

Benefits & perks

• Medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance.

Why this role

Eligible for discretionary bonus based on financial performance.

About the employer

Teradyne is hiring for this role. Industry: Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals. Sector: 33.