ASIC Design Intern — SoC Design

Job overview

The ASIC Design Intern role is onsite in San Jose, CA, for a six-month internship at 40 hours per week. Compensation is $35–$45 per hour. The intern joins SK hynix memory solutions America’s System on Chip Design Team, which develops controllers for high-performance SSDs and next-generation enterprise and AI data-center storage. The intern contributes to the design cycle by developing RTL for IP and collaborating with verification, silicon validation, and firmware teams. This work supports design quality for the team’s storage solutions.

What you'll do

• Design RTL in Verilog or SystemVerilog for IP based on existing modules or new specifications
• collaborate with Design Verification, Silicon Validation, and Firmware teams
• create clear documentation and communication.

What we're looking for

Skills & competencies

asic design intern

soc design

san jose ca

sk hynix

$35–$45/hr

six-month internship

40 hours per week

rtl design

verilog

systemverilog

high-performance ssds

semiconductor

Work arrangement

• Weekend coverage required

Why this role

Six-month internship; 40 hours per week; start date listed as immediately (November 2026/December 2026); currently enrolled in a BS, MS, or PhD program in Electrical Engineering, Computer Engineering, or a related field required.

About the employer

SK hynix memory solutions America Inc. is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.