Senior FPGA Design Engineer (San Jose, CA)
Compensation
$170k – $273k /yr
Employment type
Full-time
Work setting
On-site
Location
San Jose, CA
Schedule
Day shift
Posted
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Job overview
The Senior FPGA Design Engineer is an onsite role based in San Jose, CA, with a salary range of $170,400–$272,600 USD per year. This position supports the development of memory test solutions. This role exists to architect and implement FPGA solutions for test instrumentation. It contributes to the company's goals by delivering high-quality, reliable designs for advanced memory technologies.
What you'll do
- Architect/implement FPGA solutions
- provide technical guidance
- turn requirements into reliable designs
- maintain existing designs
- maintain schedule commitments.
What we're looking for
- Skills & competencies
- full-timeday shiftsan jose cateradynefpgadesign engineeringmemory testsemiconductoronsiteno on-call$170k-$272k/yr
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, dental, vision, FSA, retirement savings, life/disability insurance, paid vacation/holidays, tuition assistance.
Why this role
Requires 8+ years of relevant experience in FPGA design.
About the employer
Teradyne is hiring for this role. Industry: Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals. Sector: 33.
Additional details
- Industry sector
- 33
- Industry
- Instrument Manufacturing for Measuring and Testing Electricity and Electrical Signals
- Occupation code
- 15-1252.00
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Listing ID: 2daf8cea-f0f2-4590-a3ea-5c773403ee69