Senior Design Verification Engineer

Job overview

The Senior Design Verification Engineer role is onsite in San Jose, CA, with compensation of $65 per hour. The engineer supports development and verification of high-performance IP, including compute arrays, DMA engines, Networks-on-Chip, crossbars, and memory subsystems. The role develops and maintains scalable SystemVerilog/UVM verification environments and drives functional, performance, and system-level verification. It contributes to project delivery by analyzing regressions, closing coverage, identifying performance bottlenecks, and collaborating with design, architecture, and verification teams.

What you'll do

• Develop and maintain scalable SystemVerilog/UVM verification environments and testbenches
• verify AXI interfaces, NoC and crossbar architectures, DMA engines, compute arrays, and memory subsystems
• develop verification strategies
• execute regression testing and perform failure triage, debugging, and root-cause analysis
• drive functional and code coverage closure
• identify performance bottlenecks
• collaborate across engineering teams
• provide progress updates to customer and project stakeholders.

What we're looking for

Skills & competencies

senior design verification engineer

san jose ca

nesco resource

full-time

$65/hr

systemverilog

uvm

asic verification

soc verification

axi protocols

coverage closure

dma and noc

Work arrangement

• Weekend coverage required

Benefits & perks

• Medical, vision, dental, 401(k), and Employee Assistance Program services.

Why this role

The posting seeks 5–15 years of relevant experience and a bachelor’s or master’s degree in electrical engineering, computer engineering, computer science, or a related discipline. SystemVerilog, UVM, AXI, and performance-focused verification experience are required.

About the employer

Nesco Resource, LLC is hiring for this role. Industry: Engineering Services. Sector: 54.