ASIC/FPGA Methodology Engineer
Compensation
$155k – $248k /yr
Employment type
Full-time
Work setting
On-site
Location
North Reading, MA
Schedule
Day shift
Posted
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Job overview
The ASIC/FPGA Methodology Engineer is an onsite role based in North Reading, MA, supporting Teradyne's test and automation technology team. The base salary range is $154,900 to $247,800 per year, and the role focuses on defining and maintaining workflows for hardware design and verification. This position exists to optimize design flows and implement CI/CD pipelines to streamline development processes. By providing technical guidance and utilizing modern development tools, the engineer ensures that Teradyne's test technology continues to power next-generation electronic devices efficiently.
What we're looking for
- Skills & competencies
- full-timeday shiftnorth reading materadyneasicfpgamethodologyhardware designci/cd$154k-$247k
- Work arrangement
- Weekend coverage required
Benefits & perks
- Medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation, holidays, and tuition assistance.
About the employer
Teradyne is hiring for this role. Industry: Engineering Services. Sector: 54.
Additional details
- Industry sector
- 54
- Industry
- Engineering Services
- Occupation code
- 15-1252.00
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Listing ID: 24228e36-16f7-4364-b570-df2091868535