Verification Engineer

Job overview

The Verification Engineer role is onsite in Austin, TX. Compensation is not specified. The position supports formal verification work using Synopsys VC Formal and/or Cadence Jasper Gold tools. The role applies formal verification methods to design verification, including property specification, connectivity and register checks, equivalence checking, and coverage analysis. Scripting supports automation of verification flows.

What you'll do

• Use VC Formal and/or Jasper Gold
• develop SystemVerilog Assertions and formal properties
• perform formal property verification, connectivity checking, register verification, equivalence checking, and coverage analysis
• use TCL, Python, or Perl for flow automation. SystemVerilog and UVM experience are nice to have.

What we're looking for

Skills & competencies

verification engineer

formal verification

systemverilog assertions

sva

vc formal

jasper gold

connectivity checking

register verification

equivalence checking

coverage analysis

tcl

python

austin tx

saicon consultants

Work arrangement

• Weekend coverage required

Why this role

Hands-on formal verification experience with VC Formal or Jasper Gold.

About the employer

Saicon Consultants Inc is hiring for this role. Industry: Employment Placement Agencies. Sector: 56.