Principal Design Verification Engineer

Job overview

The Principal Design Verification Engineer role is onsite in San Jose, CA. Compensation is not specified. The role supports verification of Renesas Electronics’ next-generation semiconductor memory interface products, including data buffer silicon and DDR6 technology. The engineer leads verification strategy and execution for complex digital designs, working with design teams to identify issues and confirm functionality, performance, and product requirements. The work advances verification quality, reuse, and readiness through planning, implementation, debugging, and signoff.

What you'll do

• Lead block- and system-level verification strategy and execution
• define methodologies, test plans, coverage strategies, and environments
• develop and optimize SystemVerilog/UVM testbenches
• drive test development, functional coverage, checkers, constrained-random verification, and coverage closure
• own verification from planning through signoff
• collaborate with RTL and design engineers
• analyze specifications and results
• debug complex failures
• develop reusable components and best practices
• guide and mentor verification engineers
• communicate progress, risks, and readiness.

What we're looking for

Skills & competencies

principal design verification engineer

san jose ca

renesas electronics

semiconductor

systemverilog

uvm

ddr6

memory interfaces

digital design

verification strategy

technical leadership

Work arrangement

• Weekend coverage required

Benefits & perks

• Competitive benefits package
• details provided during the hiring process.

Why this role

Requires a bachelor's or master's degree in a related technical field, extensive semiconductor design verification experience, expert SystemVerilog proficiency, and significant UVM experience. DDR or memory experience is advantageous but not required.

About the employer

Renesas Electronics is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.