Principal ASIC Design Engineer

Job overview

The Principal ASIC Design Engineer role is onsite in Folsom, CA. The stated base salary range is $186,000–$407,000 per year, with additional compensation potentially including benefits, bonuses, and equity. The role is part of Micron’s Interface Pathfinding team, which validates novel PHY solutions for future high-speed interfaces. As the primary digital contributor on a small senior team, this engineer owns digital block architecture and RTL through synthesis, timing, verification support, and handoff to implementation. The work advances high-speed interface technologies from architecture toward tape-out and supports Micron’s memory and storage innovation.

What you'll do

• Own micro-architecture and synthesizable SystemVerilog RTL for digital soft IP
• define architecture specifications, interface documents, CDC strategy, and SDC constraints
• execute synthesis and static timing analysis
• coordinate digital/analog integration and serve as the digital interface to layout
• support scan, DFT, verification, simulation, and lab bring-up
• maintain design and implementation documentation.

What we're looking for

Skills & competencies

principal asic design engineer

asic design

systemverilog

rtl

high-speed phy

digital design

synthesis

static timing analysis

folsom ca

micron

$186k–$407k/year

Work arrangement

• Weekend coverage required

Benefits & perks

• Medical, dental, and vision plan options
• income-protection programs
• paid family leave
• paid time off and holidays.

Why this role

Primary digital ownership on a deliberately small, senior team developing silicon validation for novel high-speed PHY solutions.

About the employer

Micron Technology, Inc. is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.