Static Timing Analysis (STA) Engineer

Job overview

The Static Timing Analysis (STA) Engineer is an onsite role in Santa Clara, CA, with a salary range of $153,200 to $229,800 per year. This role is part of the Integrated Wireless Technology team, focusing on timing closure and synthesis for low-power Wi-Fi SoCs. The engineer will drive timing-critical implementation for high-performance connectivity chipsets used in mobile, IoT, and automotive platforms. The role involves close collaboration with RTL design, physical design, and verification teams to ensure robust silicon delivery on aggressive schedules.

What you'll do

• Drive subsystem-level STA and timing closure for pre- and post-layout phases.
• Perform timing analysis using PrimeTime.
• Identify timing bottlenecks and debug violations.
• Develop and validate SDC constraints.
• Manage large-scale multi-corner/multi-mode STA runs.
• Perform synthesis and formal verification.

What we're looking for

Skills & competencies

contract

day shift

santa clara ca

sta

synthesis

asic

soc

wi-fi

timing closure

qualcomm

$153k-$230k

onsite

no on-call

no travel

Work arrangement

• Weekend coverage required

Benefits & perks

• Competitive annual discretionary bonus program, annual RSU grants, and comprehensive US benefits package.

Why this role

Specialized focus on timing closure for complex, low-power wireless connectivity SoCs.

About the employer

Qualcomm is hiring for this role. Industry: Engineering Services. Sector: 54.