Principal Digital Verification Engineer — Memory Interface

Job overview

The Principal Digital Verification Engineer — Memory Interface role is onsite in Plano, TX; compensation is not specified. The role supports Renesas memory interface products used in data centers for artificial intelligence and cloud computing. The engineer drives verification of leading-edge memory data buffer chips, including DDR5 and future generations, to ensure functional and performance requirements are met. The role develops verification strategy and test plans, monitors coverage, improves test environments, and provides technical guidance to verification engineers.

What you'll do

• Verify DDR5 data buffer functionality and performance
• integrate and test at system and block levels using UVM
• participate in feasibility studies
• develop verification plans, tests, coverage, and checkers
• build reusable verification environments
• optimize UVM testbenches
• own assigned verification environments and tools
• guide engineers
• collaborate with design teams
• report progress to management.

What we're looking for

Skills & competencies

full-time

principal engineer

digital verification

memory interface

ddr5

ddr6

uvm

semiconductors

plano tx

renesas electronics

verification planning

design coverage

Work arrangement

• Weekend coverage required

Benefits & perks

• Renesas describes a competitive benefits package
• details are provided during the hiring process.

Why this role

Focuses on memory data buffer chips for data-center AI and cloud computing applications.

About the employer

Renesas Electronics is hiring for this role. Industry: Semiconductor and Related Device Manufacturing. Sector: 33.